AMD's Next-Gen RDNA 5 Graphics Architecture: Debunking CU Count Rumors and Memory Innovations

The next generation of AMD's graphics processing units, potentially dubbed RDNA 5 or UDNA, is generating significant buzz, with conflicting reports circulating regarding its core specifications. Early unconfirmed details hinted at a powerful high-end model boasting 192 Compute Units, yet more recent leaks from reputable sources suggest a different computational configuration. This evolving narrative prompts a closer examination of how AMD might be reinterpreting its CU metrics. Furthermore, intriguing information has emerged about the potential adoption of laptop-grade memory, LPDDR5X, for more accessible GPUs, indicating a strategic shift in memory technology to achieve optimal bandwidth.

Initial reports from sources like the YouTube channel Moore's Law is Dead outlined a quartet of chips for AMD's RDNA 5 series, internally referred to as AT0, AT2, AT3, and AT4. These were initially pegged with respective maximum CU counts of 192, 80, 48, and 24. However, a contrasting revelation from Kepler_L2 presented revised block diagrams showing these figures halved, suggesting 96, 40, 24, and 12 CUs. At first glance, this reduction appears perplexing, especially considering that AMD's current high-end RDNA 3 GPU, the Radeon RX 7900 XTX, already features 96 CUs, and the current Radeon RX 9060 XT has 32 CUs. Such a decrease for the next generation seems counterintuitive.

The most plausible explanation reconciles these seemingly contradictory reports: AMD may be redefining what constitutes a \"Compute Unit\" in RDNA 5. Historically, an RDNA CU was equivalent to a Work Group Processor (WGP), which itself contained two CUs. If AMD has decided to align the WGP and CU definitions for RDNA 5, then 96 new-measure CUs would indeed correspond to the previously rumored 192 old-measure CUs. This reinterpretation would mean that the flagship AT0 GPU remains a formidable component, and lower-end models, like the replacement for the 9060 XT, would effectively see a substantial increase in computational power.

It is important to note that the maximum CU counts might not directly translate to the actual specifications of gaming GPUs released to the market. For instance, while the AT0 might theoretically support 192 (old measure) CUs, the actual top-tier gaming card could be a slightly scaled-back version, perhaps with 154 old-style CUs. Even so, this still represents a significant leap from current offerings. Beyond raw CU numbers, RDNA 5 is also anticipated to deliver substantial advancements in ray tracing and path tracing capabilities, promising a noticeable performance enhancement in modern gaming environments.

Further details suggest a noteworthy memory strategy for the lower-end GPUs. While the AT2 is shown with fewer memory controllers, the AT3 and AT4 models are rumored to utilize LPDDR5X laptop memory instead of traditional GDDR6 or GDDR7 graphics memory. To compensate for the inherent bandwidth differences, these chips are expected to feature wider memory buses, potentially 256-bit or 384-bit. This approach, while unusual for discrete graphics cards, mirrors AMD's design in its Strix Halo laptop APU, which also employs a 256-bit LPDDR5X bus, indicating a viable solution for achieving necessary bandwidth without resorting to larger, more power-hungry memory types. While these details remain unconfirmed, the emerging picture suggests AMD is poised to offer a comprehensive range of gaming GPUs, embracing innovative architectural and memory solutions to meet the demands of the next generation.